1. Field of the Invention
The present invention relates generally to a system and a method for controlling a re-assembling buffer. More specifically, the invention relates to a system and a method for controlling a re-assembling queue buffer for re-assembling cells in a transmission system, in which CBR (Constant Bit Rate) data is transmitted in a form of a cell.
2. Description of the Related Art
In an ATM (Asynchronous Transfer Mode) communication, there are functions, in which the CBR data to be transmitted is formed into an ATM cell data of a constant bit length, these ATM cells arc transmitted to a TDM (Time Division Multiplex) transmission line as a TDM transmission data, and a TDM reception data is received from the TDM transmission line as the ATM cell. Such functions are referred to as CLAD (Cell Assembly and Disassembly) function, which has been defined in ITU-T as one function of an ATM adaptation layer.
In the ATM adaptation layer, there are a re-assembling function (on the basis of the protocol defined in AAL1) for converting the ATM cell into the TDM transmission data, and conversely assembling function (on the basis of the protocol defined in AAL1) for converting TDM data into the ATM cell.
FIG. 3 is a block diagram showing re-assembling/assembling function, the reception ATM cells (Cell) are sequentially received in first-in first-out manner in a re-assembling queue buffer 1 and then input to a re-assembling portion 2 with accommodating delay fluctuation amount of respective cells. Thus, the data is re-assembled to be transmitted to the TDM transmission line as the TDM transmission data.
On the other hand, the TDM reception data received from the TDM transmission line are assembled by an assembling portion 3 into the ATM cells to be transmitted.
In the conventional construction shown in FIG. 3, a storage depth of the re-assembling queue buffer 1 for accommodating delay fluctuation of the ATM cell is typically fixed. The delay fluctuation of the ATM cell to be accommodated by the re-assembling queue buffer 1 depends on parameters of number of nodes through which the cell passes, delay fluctuation amount of respective node, line speed and so forth.
Thus, fluctuation of the cell delay amount depending upon various parameters requires variation of the storage depth of the re-assembling queue buffer 1 to accommodate the delay amount depending upon fluctuation. In the alternative, in case where the storage depth of the re-assembling queue buffer cannot be varied, the storage depth of the buffer has to be set to be large enough to accommodate the possible maximum delay fluctuation amount.
The storage depth of the re-assembling queue buffer 1 is the significant factor for defining data transmission delay. In order to reduce the data transmission delay in system, it is required to make the storage depth of the buffer smaller.
Thus, the storage depth of the re-assembling queue buffer should compromise accommodation of delay fluctuation amount of the reception ATM cell and shortening data transmission delay period.